Forum Post: RE: Clarification in MDIO bus driver & working of ethernet

Hi Bob,

Yes, it seems it is related to external PHY. I would post my method and list of changes here in sometime.

Hi Schuyler,

Kindly check the register dump of TLK110. To me other things look normal except that in extended register 0x0011 (PHYSCR) bit 0 and bit 1 are set (1) whereas the default value for these bits are 0 and i am not writing anything on these bits at all in the kernel.

___________________________Register Dump_________________________________ Register address       Value     0x0000            0x3100     0x0001            0x7849     0x0002            0x2000     0x0004            0x01e1     0x0005            0x0000     0x0006            0x0004     0x0007            0x2001     0x0008            0x0000     0x0009            0xfc01     0x000A            0x0105     0x000B            0x0000 
Extended Registers

E0x0010:- 0x0002 E0x0011:- 0x010b E0x0012:- 0x0000 E0x0013:- 0x0000 E0x0014:- 0x0000 E0x0015:- 0x0000 E0x0016:- 0x0100 E0x0017:- 0x0021 E0x0018:- 0x0400 E0x0019:- 00x8021 E0x001A:- 0x0000 E0x001C:- 0x007d 

Thanks and Regards,

Prateek