Hello Hans,
We are extremely sorry that we could not find the issue that you have reported and thankful that you have posted the solution to the problem.
When you had reported this issue sometime in November, I had run the 02.00.01.01 version of the code on our EVM and found that ISR was not being visited at the required rate. From the code base released by us , we do not enable the prescaler input clock and hence it was not deemed necessary to disable the presclaer . If you verify the value of
Timer Control Register (TCLR) it would be 0x03 implying that the timer mode is AR and the timer is running. Prescler clock is disabled by default. Clock input to the dmtimer module can be varied by either using the prescaler or by using the PRCM clock selection mux. I had check with max values for the mux and prescler disabled.
I checked out the timer input clock selection MUX value in the PRCM module . After setting it to CLK_M_OSC I had tried to run our example and failed to get the desired output. With reference to TRM
CLKSEL_TIMER2_CLK register , CLKSEL field defaults to 1 on reset.
I still do not have any explanation as to why disabling the prescaler would get the timer working.