I have resolved this issue. In an effort to help others I will list my findings.
The interrupts on the AM1806 appear to be edge triggered not level triggered. If a second interrupt from the UART occurs while you are in the ISR for the UART that second interrupt will be missed and when the ISR completes the UART will have a pending interrupt but the AM1806 interrupt controller will not respond. This condition can still happen even if check for a pending interrupt while in the ISR since the time between clearing the interrupt and exiting the ISR leaves a small window where a second interrupt can occur.
To prevent this you need to have the ISR have the highest priority possible then in the ISR the only function should be a Swi_post(). This will insure that the ISR can be completed before the first pending interrupt is serviced and a second interrupt is generated. When the SWI is run it should read the IIR and LSR to determine the cause of the interrupt and process all pending interrupts. While in the SWI if a new interrupt is generated by the UART it will force the ISR to run which will then do a second Swi_post().
With this method resolves the missing UART interrupt problem.
