Hi,
I'm still not successful...can you or anyone help me further by checking the modification in below? Is more modification required?
1.Modify bl_platform.h for the 512M nand Flash:
#define NAND_NUMOF_BLK (4096)//original 2048 in file
#define NAND_DEVICE_ID (0xDC)//original DA
2. Modify bl_platform.c for our DDR3:
#include "pin_mux.h" //under AM335x option
#define DDR3_DATA0_WR_DQS_SLAVE_RATIO_0 (0xAB)//original 3C
#define DDR3_DATA0_FIFO_WE_SLAVE_RATIO_0 (0x108)//original A5
#define DDR3_DATA0_WR_DATA_SLAVE_RATIO_0 (0xE3)//original 74
#define DDR3_DATA0_WR_DQS_SLAVE_RATIO_1 (0xAB)//original 3C in file
#define DDR3_DATA0_FIFO_WE_SLAVE_RATIO_1 (0x108)//original A5
#define DDR3_DATA0_WR_DATA_SLAVE_RATIO_1 (0xE3)//original 74
#define DDR3_EMIF_SDRAM_CONFIG (0x61C04AB2) //original ...BB2
Above is refer to our customised board working .gel file:
#define DATA_PHY_RD_DQS_SLAVE_RATIO 0x3B
#define DATA_PHY_FIFO_WE_SLAVE_RATIO 0x108 //RD DQS GATE
#define DATA_PHY_WR_DQS_SLAVE_RATIO 0xAB
#define DATA_PHY_WR_DATA_SLAVE_RATIO 0xE3 //WRITE DATA
#define DDR_IOCTRL_VALUE (0x18B)
//******************************************************************
//EMIF parameters
//******************************************************************
#define ALLOPP_DDR3_READ_LATENCY 0x06 //RD_Latency = (CL + 2) - 1
#define ALLOPP_DDR3_SDRAM_TIMING1 0x0888A39B
#define ALLOPP_DDR3_SDRAM_TIMING2 0x26337FDA
#define ALLOPP_DDR3_SDRAM_TIMING3 0x501F830F
#define ALLOPP_DDR3_SDRAM_CONFIG 0x61C04AB2 //termination = 1 (RZQ/4)
//dynamic ODT = 2 (RZQ/2)
//SDRAM drive = 0 (RZQ/6)
//CWL = 0 (CAS write latency = 5)
//CL = 2 (CAS latency = 5)
//ROWSIZE = 5 (14 row bits)
//PAGESIZE = 2 (10 column bits)