Dear Biser, this is not a Linux question (I am using Windows EC7), but a question regarding the GMPC-ECC-BCH and ELM interaction. If it was in my power, I would contact the ASIC designer of the ELM and ECC engines, or the person who wrote the AM3352 TRM datasheet Section 7.1.3.3.12.3.3. -- Did the ECC-BCH and ELM PAGE MODE designer take into account the needs of the ROM Boot Loader (so we can use ONE spare area scheme throughout the whole NAND) ? -- Regards, Anja
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