Hi Mario,
[quote user="Mario Giovanni Casali"]
Well, you can see that all memory areas (both external SRAM and on-chip RAM and external DDR) have the same attribute 0x___00E0E, that is bufferable, cachable, not shareable and "implementation" (?).
It seems that your recommendation for regular memory is not followed by the builder ("shareable" is not set and "not executable"is not set for memory areas I defined as RW); what about that?
May I have problems with DMA trasfers (from SPI Flash to memory) if the target memory area is not shareable? I had to disable data caching in order to have correct results ...
[/quote]
Wanted to add one point about marking memory as "shareable". You want to be careful when marking normal memory (data & code) as shareable. On Cortex-A8, I believe a memory region marked as cacheable and sharable is not held in the cache and therefore marking memory as shareable can result in a performance hit.
Best,
Ashish