Still cannot receive any Ethernet packets. After fixing the phy reset, we verified all the Micrel KS8721BL phy registers are set correctly, but we are still getting 'Rx Align/Code Errors' and 'Rx Fragments'. If you look at the CPSW stats register 0x4A100900:
Gives the following table:
| Populated ALE table with phy fix | ||
| 0 | Good Rx Frames | 0x00000000 |
| 4 | Broadcast Rx Frames | 0x00000000 |
| 8 | Multicast Rx Frames | 0x00000000 |
| 0C | Pause Rx Frames | 0x00000000 |
| 10 | Rx CRC Errors | 0x00000000 |
| 14 | Rx Align/Code Errors | 0x00000D3D |
| 18 | Oversize Rx Frames | 0x00000000 |
| 1C | Rx Jabbers | 0x00000000 |
| 20 | Undersize (Short) Rx Frames | 0x00000000 |
| 24 | Rx Fragments | 0x0000040F |
| 30 | Rx Octets | 0x00000000 |
| 34 | Good Tx Frames | 0x00000004 |
| 38 | Broadcast Tx Frames | 0x00000004 |
| 3C | Multicast Tx Frames | 0x00000000 |
| 40 | Pause Tx Frames | 0x00000000 |
| 44 | Deferred Tx Frames | 0x00000000 |
| 48 | Collisions | 0x00000000 |
| 4C | Single Collision Tx Frames | 0x00000000 |
| 50 | Multiple Collision Tx Frames | 0x00000000 |
| 54 | Excessive Collisions | 0x00000000 |
| 58 | Late Collisions | 0x00000000 |
| 5C | Tx Underrun | 0x00000000 |
| 60 | Carrier Sense Errors | 0x00000000 |
| 64 | Tx Octets | 0x00000948 |
| 68 | Rx + Tx 64 Octet Frames | 0x00000016 |
| 6C | Rx + Tx 65–127 Octet Frames | 0x00000ACA |
| 70 | Rx + Tx 128–255 Octet Frames | 0x000001DE |
| 74 | Rx + Tx 256–511 Octet Frames | 0x00000064 |
| 78 | Rx + Tx 512–1023 Octet Frames | 0x0000001F |
| 7C | Rx + Tx 1024_Up Octet Frames | 0x00000000 |
| 80 | Net Octets | 0x0006706A |
| 84 | Rx Start of Frame Overruns | 0x00000000 |
| 88 | Rx Middle of Frame Overruns | 0x00000000 |
| 8C | Rx DMA Overruns Section | 0x00000000 |
So the broadcast frames are making it to the wire, but the Receive errors are still there. We can bring the system up under sys/bios lwip and everything is fine and the phy registers are the same. What else could be causing these receive errors? The ALE changes do not effect anything that we can see, so we think that it must be some other configuration of the CPSW.
Any ideas?
Thanks,
John C.