Forum Post: SPI errors due to cable length/propagation delay

Hi -

We use the McSPI to drive an A-to-D IC. The SPI works great, but the problem is that there is a propagation delay induced, so that there is about a 10ns difference between data being sent by the IC to the Master (Beaglebone Black). 

What is the best solution for handling this physical limitation? I do not see a way to introduce a delay before reading MISO on the McSPI. We can make the clock slower, but that reduces our chances of running at max acquisition rates.