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Forum Post: RE: H.264 encoder with barrier implementation on uncacheable memory

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Hi Andrey,

Based on output you shared, looks like input YUV data corrupted. 

Only Core 1, 2,3 slices are corrupted and core 1 slice looks fine. 

master (Core 0) shares input data pointers to slave cores and goes to barrier. Slave cores get updated data pointers once they come out of barrier using sync APIs.  Looks like this sync got failed.

To make sure above is problem, you can disable cache for  all codec shared buffer requests.

Can you make sure all input buffers & memtabs requested from codec are aligned to 256? please share your sync API implementation. If it is reproducible with standalone setup you prepared earlier please share with us..

Regards

Rama 


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