Forum Post: Enabling External Memory(DDR3) Non cacheable

Hi,

I am working on EVM 6670 multicore, I wanted to remove CACHE_wbL1d(), CACHE_invL1d().
So, I am using MAR register to make external memory(DDR3) non cacheable.
But this change increased machine cycle count by three times.

Can anyone please suggest me which is the best way to remove cache writeback and cache invalid functions?

I need to know what is the difference between cache writeback and disable cache memory(using MAR) for efficient performance?

Regards,
Shabrin