Wade,
I have studied the code in ListMP_getHead, ListMP_putHead, and ListMP_putTail. I do not see any bugs in these functions. I believe them to be correct.
From the earlier posts in this thread, I see there is some question regarding the possible corruption of the pointers in the Attrs structure. However, I don't believe any corruption can occur. I think the confusion comes about because the list pointers are embedded in the Attrs structure inside another structure called 'head'. This 'head' structure in written back and invalidated as needed. Look for the following code:
Cache_wbInv(&(obj->attrs->head), sizeof(ListMP_Elem), Cache_Type_ALL, TRUE)
The Attrs structure (which is in shared memory and accessed by both processors) has the following memory layout:
Attrs
+-------------------+
00| Bits32 status |
04| SRPtr gateMpAttrs |
08| Elem head | SRPtr next
0C| | SRPtr prev
+-------------------+
Here are some notes regarding the code.
1. All access to the Attrs structure is protected by a GateMP instance. This means only one processor can modify the Attrs structure at a time.
2. After accessing the pointers, they are always written back to memory and evicted from the cache before the functions leave the gate. In other words, there cannot be a stale reference to the pointers in the cache.
3. The initial reference to the obj->attrs->head.next pointer should always be a new pull from memory because all previous references have been evicted from the cache. Adding a cache invalidate operation should not be needed.
Although it is tempting to simply add a cache invalidate operation to ListMP_getHead, I don't think it will fix any bug (as just explained) but it will add significant latency because cache operations are expensive.
Regarding the failure your are seeing, I would look at the following.
1. Make sure the SharedRegion cache configuration is correct. A typical mistake is to think that setting the SharedRegion cache property controls the memory cache behavior; it does not. This property must simply reflect the actual memory cache behavior. Use the Cache module to control the memory cache behavior.
2. The cache alignment is controled by the heap used for memory allocation. If you have configured a different heap mananger, make sure it is handling the cache alignment correctly.
~Ramsey