Forum Post: RE: Pacing of Tx-completion interrupt for SRIO DIO transfers

Hi Clinton,

Thanks for your reply.

As, I have added just one SWI and HWI in my code. It doesn't seem likely that there are other higher priority SWIs or HWIs that could delay the completion of my SWI.

I have attached a picture of SWIs and HWIs used in my code from the ROV in CCS after code execution. 'swifxn' is the SWI I added. And the HWI I added is connected to CPU interrupt 4 through CpIntc_dispatch().

Thanks.

Luke