Forum Post: RE: Pacing of Tx-completion interrupt for SRIO DIO transfers

Hi Luke,

I'm not a SYS/BIOS expert, but since you are using SWIs to post the transfers, other higher priority SWIs or HWIs could delay the competition of the SWI associated with your SRIO transfers. I will move this thread to the SYS/BIOS forum to get more insight.

Here is some more information on SWIs: http://processors.wiki.ti.com/images/d/d6/Swis.pdf

Thanks,

Clinton