They think they've found the problem. Even though the map states that there is free IRAM, 128k was allocated for L2 cache. So out of our 256k, we were trying to use 177k (2C77B was reported used for IRAM with Exception Handling enabled). I also found a warning was being reported during the build:
warning: ti.sysbios.family.c64p.Cache: "C:/ti/bios_6_35_04_50/packages/ti/sysbios/family/c64p/Cache.xs", line 497: ti.sysbios.family.c64p.Cache : Cache settings were changed in user configuration. User configuration options will override platform settings. Check your memory map to make sure that Cache does not conflict with your L1/L2 memory placement. To avoid conflicts between L1/L2 memory and cache, we recommended specifying cache sizes along with memory sizes in a platform package.
I assume if we specified the cache as stated in the warning, we would have received a linker warning instead of the program actually running and resulting in the erratic behavior we’ve noticed. I’m not familiar with CCS or SYS/BIOS (we just copied this project from another program here), any ideas on how to fix this warning?