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Forum Post: RE: SPI / EDMA and memcpy during transfer

Hi Murat,

i am with the AM3359 SPI-SLAVE. I cannot initiate the transfer.

If the am3359 has input data via SPI/EDMA, then after 10bytes the EDMA Interrupt triggers the EDMA ISR, in which i save the 10bytes input-data to rxBuffer, calculate, and modify the last 5 bytes in txBuffer (of total 30bytes) with e.g. a checksum.

CacheDataInvalidateBuff will be called at the beginning of the ISR before memcpy() the rxBuffer to a structure (to ensure memcpy() reads data from ext. memory)

The last bytes which will be written to ext. memory with memcpy() [txBuffer] don´t need a CacheDataInvalidateBuff because the data will be read from cache and written to memory (EDMA reads the txBuffer from memory)


The buffers are 64byte large.

#pragma DATA_ALIGN(txPingBuffer,64);   volatile unsigned char txPingBuffer[64]; 

For EDMA i use ping/pong paramsets and buffers, because i need two EDMA Interrupts (after 10bytes and the last completion interrupt)

In the picture you can see the first interrupt duration (start/end) in green. When the first Interrupt of one transfer (this one after 10bytes) is finish, the last instruction is memcpy(), copy the checksum at the last bytes of txBuffer. When the green line is low, the ISR is completed and there you can see (blue line) that 0x44 is sent two times.

That is the ERROR which i mean. The checksum at receiver will not be correct !!!

When the first EDMA ISR is finish, there are about 20 more bytes to be received/transmitted in one dataframe.

i assume that the SPI send two times the same data, if the interrupt occurs abput 12µs later and has a 15µs longer duration then usual. Everytime i got this error, the interrupt is a little bit later, so if i copy to the txBuffer that maybe the EDMA in this time has access to the same byte of the dataframe?

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