Hi,
Looking at SDIO CLK on the oscilloscope, it seems the clock is disabled for 1-2 cycles at the beginning and at the end of a command (command 52 read in this case, if it matters). Since the direction of the CMD pin is reversed in order for the slave to drive the pin, I was thinking the clock disabling was related to this (as a safety measure?).
I can't find this behaviour descibed in either the AM335x TRM or in the SDIO spec, so I was hoping someone here could confirm or deny.
Thanks,
Orjan