Hi!
We have programmed an SPI bare metal but we would like to have it work faster.
We enabled the Cache & MMU for better performance.
We would like to have an SPI period of less than 4us.
You can see what we achieved in the next oscillogram.
D2 is our SPI CLK and works at 48MHz.
D3 is our received data
D4 is our Chip select.
the most upper signal is a Convst for the ADC we have created a Pulse of 50ns for this from the GPIO of the beaglebone.
Do you have any idea how to have less idle time between the two cycles?
Kind Regards,
YEVDG