Javier,
You have a slight typo in your code above. The property name is 'cacheEnable', not cacheEnabled.
Don't set the cacheLineSize to zero. Just leave it out and the default will be used. Remember that cacheEnable can be different for each core, but cacheLineSize must be the same for all cores.
The SharedRegion cache configuration simply tells SharedRegion if it should issue cache operations or not. It does not actually controll the cacheability of the memory. That is done by the Cache module.
var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
Cache.setMarMeta(0x0C000000, 0x100000, Cache.Mar_DISABLE);
Although this API takes a size, the MAR registers still operate on 16 MB regions. Keep in mind that the region and size will be aligned on this boundary.
~Ramsey
