Thanks for you quick reply and suggestion. I looked through the map files of both my two SYS/BIOS applications (one for CPU1 and one for CPU2) and the blinky_dc_cpu1 and blinky_dc_cpu2 (controlsuite examples.) I did find a few issues with the .cmd file F28377D.cmd that is part of the TI Resource Explorer example project. Unfortunately changing these issues still did not fix my problem.
The issues I changed:
1. According to 2837x_FLASH_lnk_cpu1.cmd from controlsuite the first 0x120 of RAMM0 is used for BOOT rom stack. For CPU2 it is the first 0x7E for the boot room stack.
So I changed both of my cmd files for my two SYS/BIOS applications to not use RAMM0 at all.
2. The ram sections CPU2TOCPU1RAM and CPU1TOCPU2RAM have to be used properly for CPU1 and CPU2
For CPU1 my cmd file needs to read
GROUP : > CPU1TOCPU2RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}
GROUP: > CPU2TOCPU1RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}
For CPU2 you must swap the CPU?TOCPU?RAM defines as so:
GROUP : > CPU2TOCPU1RAM, PAGE = 1
{
PUTBUFFER
PUTWRITEIDX
GETREADIDX
}
GROUP: > CPU1TOCPU2RAM, PAGE = 1
{
GETBUFFER : TYPE = DSECT
GETWRITEIDX : TYPE = DSECT
PUTREADIDX : TYPE = DSECT
}
These two issues I found will probably help me out in future development, but they did not fix my current problem. What other memory regions could CPU2 have the same load addresses as CPU1? I know they share RAMGS0-GS15 but I have removed those memory sections from my CMD files to make sure I am not using that RAM.
Are there other SYS/BIOS settings, for example in the BOOT section, that need to be or should not be set for CPU2? How about in the HWI section?
Thanks
Dan